The present invention relates to a circuit for converting the integral value of an analog signal into a digital signal.
An electronic type electric energy meter for three-phase alternating current is disclosed in `INT. J. Electronics` 1980, vol. 48, No. 3, p. 257. By altering and improving this technique for single-phase use, some of the inventors of the present invention have proposed an electric power meter which is shown in FIG. 1 and which has been applied for a Japanese patent (Application No. 57-130301). This electric power meter produces a frequency signal f.sub.0 in such a way that a voltage signal E.sub.v proportional to a feeder line voltage and a voltage signal E.sub.i proportional to a feeder line current are multiplied and then integrated. Accordingly, electric energy can be obtained by counting the frequency f.sub.0.
The operations of this circuit will be described with reference to a time chart in FIG. 2.
This figure illustrates a case where the phase difference between the voltage and the current is 0.degree..
An integrator INT1, comparators CP1, CP2, a flip-flop FF1 and a switch SW1 serve to generate a triangular wave output V.sub..DELTA.. The integrator INT1 is composed of an operational amplifier A1, a resistor R1 and a capacitor C1, and it produces the integral output V.sub..DELTA. of a voltage V.sub.B or -V.sub.B applied thereto through the switch SW1. For example, when the integrator is supplied with the voltage V.sub.B, it provides a voltage which decreases rectilinearly gradually. This output V.sub..DELTA. is applied to the noninverting input end of the comparator CP1 and the inverting input end of the comparator CP2. The inverting input end of the comparator CP1 and the noninverting input end of the comparator CP2 are respectively supplied with reference voltages V.sub.R and -V.sub.R. The comparator CP1 delivers a pulse for setting the flip-flop FF1 each time the output V.sub..DELTA. equalizes to V.sub.R, while the comparator CP2 delivers a pulse for resetting the flip-flop FF1 each time the output V.sub..DELTA. equalizes -V.sub.R. The switch SW1 connects the voltage V.sub.B to the resistor R1 when the output Q of the flip-flop FF1 is "1", and it connects the voltage -V.sub.B to the resistor R1 when the output Q is "0". For example, when the switch SW1 is set on the voltage V.sub.B side, the output V.sub..DELTA. of the integrator INT1 decreases rectilinearly gradually, and upon detection of the coincidence thereof in the comparator CP2, the flip-flop FF2 is reset, so that the switch SW1 is changed-over to the -V.sub.B side by the "0" output of the flip-flop. As a result, the integral output V.sub..DELTA. begins to increase rectilinearly, and when it has coincided with +V.sub.R, the flip-flop FF1 is set by the comparator CP1. In this manner, the output V.sub..DELTA. becomes the triangular wave which oscillates between .+-.V.sub.R at a fixed period. This voltage V.sub..DELTA. and the signal of the voltage to-be-measured E.sub.v are respectively applied to the noninverting input terminal and inverting input terminal of a comparator CP3. The output V.sub.g of this comparator is a pulse whose width has been modulated in correspondence with the amplitude and phase of the signal E.sub.v. To this end, the frequency of the triangular wave V.sub..DELTA. is rendered sufficiently higher than that of the voltage E.sub.v.
When the duty ratio D of the voltage V.sub.g is defined to be the proportion of a time for which the voltage V.sub.g becomes a "high" level within one cycle period of the triangular wave V.sub..DELTA., it becomes: EQU D=1/2(1-E.sub.v /V.sub.R) (1)
That is, D=50% holds at E.sub.v =0 V, and E.sub.v &lt;0 for D&gt;0 and E.sub.v &gt;0 for D&lt;0 hold.
This output V.sub.g is used for controlling a switch SW2 through an exclusive OR gate (E-OR gate) EOR. The switch SW2 applies the signal of the current to-be-measured E.sub.i and the inverted signal thereof -E.sub.i to an integrator INT2 while changing-over them. The integrator INT2, comparators CP4, CP5 and a flip-flop FF2 are connected similarly to the integrator INT1, comparators CP1, CP2 and flip-flop FF1 mentioned above, respectively. In order to fold back the integral waveform V.sub.p of the integrator INT2 within the operating range (+V.sub.R --V.sub.R) thereof, the output S.sub.v of the flip-flop FF2 is applied to the E-OR gate EOR so as to invert the voltage V.sub.g. Accordingly, when the signal S.sub.v is "0", the output of the gate EOR becomes a pulse whose width has been modulated in correspondence with the signal E.sub.v, and when the signal S.sub.v is "1", it becomes a pulse whose width has been modulated in correspondence with the inverted signal of the signal E.sub.v.
The flip-flop FF2 is set or reset by the output of the comparator CP4 or CP5 which is provided when the output V.sub.p of the integrator INT2 has exceeded the range of .+-.V.sub.R. At this time, the output S.sub.v becomes its "high" or "low" level. Assuming that the outputs of the CP4 and CP5 are alternately provided without fail (this holds when the phase difference between the voltage and the current is 0), the duty ratio D.sub.I between the voltage V.sub.g and the EOR output S.sub.I of the voltage S.sub.v takes the value of D.sub.I =D or D.sub.I =1-D, depending upon whether the pulse S.sub.v is at the "low" level or "high" level. In case of allotting the value "0" to the output S.sub.v when it is at the "low" level and the value "1" thereto when it is at the "high" level, the duty ratio is expressed as D.sub.I =S.sub.v +(1-2S.sub.v)D. When the switch SW2 is changed-over by the signal S.sub.I thus obtained, the output V.sub.M of the switch SW2 is proportional to the product between the signals E.sub.v and E.sub.i, as viewed on the average.
The average value V.sub.M of the output V.sub.M within one cycle of the triangular wave V.sub..DELTA. becomes: ##EQU1## Further, by substituting Formula (1), it becomes: ##EQU2## Since (2S.sub.v -1) is -1 for S.sub.v =0 and is +1 for S.sub.v =1, Formula (2) becomes: ##EQU3## That is, the value V.sub.M is proportional to the instantaneous voltages, and its sign changes between plus and minus, depending upon the signal S.sub.v.
V.sub.p is the integral of V.sub.M, and is given by: ##EQU4## where V.sub.po denotes the initial value of the integration.
It is detected by the comparators CP4 and CP5 that V.sub.p has reached .+-.V.sub.R, with the result that the status of the flip-flop FF2 changes. When the number of times which the output S.sub.v of the flip-flop FF2 has become "1" is counted for a certain period of time, a value proportional to electric energy can be obtained. For example, let's consider a time section from t=0 to t=T. Herein, the output V.sub.p changes between .+-.V.sub.R with a waveform as shown in FIG. 2. E.sub.v .times.E.sub.i &gt;0 is considered, and V.sub.p0 =-V.sub.R and S.sub.v =0 are supposed at t=0. Timings at which V.sub.p thereafter collides against +V.sub.R are denoted by t.sub.1, t.sub.3, t.sub.5 . . . and t.sub.2n-1, and timings at which it collides against -V.sub.R are denoted by t.sub.2, t.sub.4 . . . and t.sub.2n. Then, in sections t.sub.2i -t.sub.2i+1, S.sub.v =0 holds, so that: ##EQU5## In addition, in sections t.sub.2i+1 -t.sub.2i+2, S.sub.v =1 holds, so that: ##EQU6## Accordingly, the variation V.sub.T of the output voltage under the assumption that the integrator output is integrated continuously without folding it back becomes: ##EQU7##
On the other hand, the number of pulses of the output S.sub.v in this section is n. Accordingly, ##EQU8## where ##EQU9## denotes the electric energy during the time interval T. Thus, the value obtained by counting the output S.sub.v is proportional to the electric energy.
A case where a phase difference has arisen between the voltage and the current in this circuit will now be considered in connection with an example in FIG. 3. Here, the phase difference is assumed .theta.=45.degree.. Since the pulses V.sub.g and V.sub.M have been elucidated in FIG. 2, it is supposed here that E.sub.v .times.E.sub.i with the modulation waveform averaged is inputted to the integrator INT2. Then, a waveform as indicated at .circle.a in the figure can appear in the integrator output V.sub.p. This is a phenomenon which can take place when E.sub.v .times.E.sub.i &lt;0 has held, and which is attributed to the fact that an amplifier A2 is saturated, so the integrator fails to operate. When enlarged, this part is as shown in FIG. 4. Indicated by a broken line in the figure is the waveform V.sub.p ' of the output V.sub.p in the case of assuming that the amplifier A2 is an ideal one which is not saturated. Even after the recovery of the amplifier from the saturation, the actual output V.sub.p does not become superposed on the waveform V.sub.p ', and the difference develops as an error. The output of the operational amplifier can change to the vicinity of a supply voltage, but cannot exceed the supply voltage. Accordingly, when the input side is subjected to a condition under which the output exceeds the supply voltage range, the amplifier becomes saturated with its output fixed to the vicinity of the supply voltage and fails to effect the function as such. Since .+-.V.sub.R are set inside the range of the supply voltages in FIG. 3, the output is fixed near the supply voltage as shown at .circle.a when the amplifier becomes saturated. The reason why the integrator becomes saturated in this manner, is as stated below. As the proper operation, the pulses of the comparators CP4 and CP5 ought to be alternately provided to invert the signal S.sub.v so as to fold back the output V.sub.p. However, when the direction of the output V.sub.p reverses midway as shown in FIG. 3, the pulses of the comparator CP4 or CP5 are continuously provided, and hence, it becomes impossible to invert the signal S.sub.v. This phenomenon is more noticeable as the phase difference is greater and as the time constant C.sub.2 .times.R.sub.2 of the integrator INT2 is smaller.
In this manner, the circuit in FIG. 1 has the disadvantage that electric power having a phase difference cannot be precisely measured.